2 * Copyright (c) 1994,1995 Stefan Esser, Wolfgang StanglMeier
3 * Copyright (c) 2000 Michael Smith <msmith@freebsd.org>
4 * Copyright (c) 2000 BSDi
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
35 * PCI:PCI bridge support.
38 #include <sys/param.h>
40 #include <sys/kernel.h>
41 #include <sys/malloc.h>
42 #include <sys/module.h>
44 #include <sys/sysctl.h>
45 #include <sys/systm.h>
47 #include <dev/pci/pcivar.h>
48 #include <dev/pci/pcireg.h>
49 #include <dev/pci/pci_private.h>
50 #include <dev/pci/pcib_private.h>
54 static int pcib_probe(device_t dev);
55 static int pcib_suspend(device_t dev);
56 static int pcib_resume(device_t dev);
57 static int pcib_power_for_sleep(device_t pcib, device_t dev,
59 static uint16_t pcib_ari_get_rid(device_t pcib, device_t dev);
60 static uint32_t pcib_read_config(device_t dev, u_int b, u_int s,
61 u_int f, u_int reg, int width);
62 static void pcib_write_config(device_t dev, u_int b, u_int s,
63 u_int f, u_int reg, uint32_t val, int width);
64 static int pcib_ari_maxslots(device_t dev);
65 static int pcib_ari_maxfuncs(device_t dev);
66 static int pcib_try_enable_ari(device_t pcib, device_t dev);
68 static device_method_t pcib_methods[] = {
69 /* Device interface */
70 DEVMETHOD(device_probe, pcib_probe),
71 DEVMETHOD(device_attach, pcib_attach),
72 DEVMETHOD(device_detach, bus_generic_detach),
73 DEVMETHOD(device_shutdown, bus_generic_shutdown),
74 DEVMETHOD(device_suspend, pcib_suspend),
75 DEVMETHOD(device_resume, pcib_resume),
78 DEVMETHOD(bus_read_ivar, pcib_read_ivar),
79 DEVMETHOD(bus_write_ivar, pcib_write_ivar),
80 DEVMETHOD(bus_alloc_resource, pcib_alloc_resource),
82 DEVMETHOD(bus_adjust_resource, pcib_adjust_resource),
83 DEVMETHOD(bus_release_resource, pcib_release_resource),
85 DEVMETHOD(bus_adjust_resource, bus_generic_adjust_resource),
86 DEVMETHOD(bus_release_resource, bus_generic_release_resource),
88 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
89 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
90 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
91 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
94 DEVMETHOD(pcib_maxslots, pcib_ari_maxslots),
95 DEVMETHOD(pcib_maxfuncs, pcib_ari_maxfuncs),
96 DEVMETHOD(pcib_read_config, pcib_read_config),
97 DEVMETHOD(pcib_write_config, pcib_write_config),
98 DEVMETHOD(pcib_route_interrupt, pcib_route_interrupt),
99 DEVMETHOD(pcib_alloc_msi, pcib_alloc_msi),
100 DEVMETHOD(pcib_release_msi, pcib_release_msi),
101 DEVMETHOD(pcib_alloc_msix, pcib_alloc_msix),
102 DEVMETHOD(pcib_release_msix, pcib_release_msix),
103 DEVMETHOD(pcib_map_msi, pcib_map_msi),
104 DEVMETHOD(pcib_power_for_sleep, pcib_power_for_sleep),
105 DEVMETHOD(pcib_get_rid, pcib_ari_get_rid),
106 DEVMETHOD(pcib_try_enable_ari, pcib_try_enable_ari),
111 static devclass_t pcib_devclass;
113 DEFINE_CLASS_0(pcib, pcib_driver, pcib_methods, sizeof(struct pcib_softc));
114 DRIVER_MODULE(pcib, pci, pcib_driver, pcib_devclass, NULL, NULL);
117 SYSCTL_DECL(_hw_pci);
119 static int pci_clear_pcib;
120 TUNABLE_INT("hw.pci.clear_pcib", &pci_clear_pcib);
121 SYSCTL_INT(_hw_pci, OID_AUTO, clear_pcib, CTLFLAG_RDTUN, &pci_clear_pcib, 0,
122 "Clear firmware-assigned resources for PCI-PCI bridge I/O windows.");
125 * Is a resource from a child device sub-allocated from one of our
129 pcib_is_resource_managed(struct pcib_softc *sc, int type, struct resource *r)
135 return (rman_is_region_manager(r, &sc->bus.rman));
138 return (rman_is_region_manager(r, &sc->io.rman));
140 /* Prefetchable resources may live in either memory rman. */
141 if (rman_get_flags(r) & RF_PREFETCHABLE &&
142 rman_is_region_manager(r, &sc->pmem.rman))
144 return (rman_is_region_manager(r, &sc->mem.rman));
150 pcib_is_window_open(struct pcib_window *pw)
153 return (pw->valid && pw->base < pw->limit);
157 * XXX: If RF_ACTIVE did not also imply allocating a bus space tag and
158 * handle for the resource, we could pass RF_ACTIVE up to the PCI bus
159 * when allocating the resource windows and rely on the PCI bus driver
163 pcib_activate_window(struct pcib_softc *sc, int type)
166 PCI_ENABLE_IO(device_get_parent(sc->dev), sc->dev, type);
170 pcib_write_windows(struct pcib_softc *sc, int mask)
176 if (sc->io.valid && mask & WIN_IO) {
177 val = pci_read_config(dev, PCIR_IOBASEL_1, 1);
178 if ((val & PCIM_BRIO_MASK) == PCIM_BRIO_32) {
179 pci_write_config(dev, PCIR_IOBASEH_1,
180 sc->io.base >> 16, 2);
181 pci_write_config(dev, PCIR_IOLIMITH_1,
182 sc->io.limit >> 16, 2);
184 pci_write_config(dev, PCIR_IOBASEL_1, sc->io.base >> 8, 1);
185 pci_write_config(dev, PCIR_IOLIMITL_1, sc->io.limit >> 8, 1);
188 if (mask & WIN_MEM) {
189 pci_write_config(dev, PCIR_MEMBASE_1, sc->mem.base >> 16, 2);
190 pci_write_config(dev, PCIR_MEMLIMIT_1, sc->mem.limit >> 16, 2);
193 if (sc->pmem.valid && mask & WIN_PMEM) {
194 val = pci_read_config(dev, PCIR_PMBASEL_1, 2);
195 if ((val & PCIM_BRPM_MASK) == PCIM_BRPM_64) {
196 pci_write_config(dev, PCIR_PMBASEH_1,
197 sc->pmem.base >> 32, 4);
198 pci_write_config(dev, PCIR_PMLIMITH_1,
199 sc->pmem.limit >> 32, 4);
201 pci_write_config(dev, PCIR_PMBASEL_1, sc->pmem.base >> 16, 2);
202 pci_write_config(dev, PCIR_PMLIMITL_1, sc->pmem.limit >> 16, 2);
207 * This is used to reject I/O port allocations that conflict with an
211 pcib_is_isa_range(struct pcib_softc *sc, u_long start, u_long end, u_long count)
215 if (!(sc->bridgectl & PCIB_BCR_ISA_ENABLE))
218 /* Only check fixed ranges for overlap. */
219 if (start + count - 1 != end)
222 /* ISA aliases are only in the lower 64KB of I/O space. */
226 /* Check for overlap with 0x000 - 0x0ff as a special case. */
231 * If the start address is an alias, the range is an alias.
232 * Otherwise, compute the start of the next alias range and
233 * check if it is before the end of the candidate range.
235 if ((start & 0x300) != 0)
237 next_alias = (start & ~0x3fful) | 0x100;
238 if (next_alias <= end)
244 device_printf(sc->dev,
245 "I/O range %#lx-%#lx overlaps with an ISA alias\n", start,
251 pcib_add_window_resources(struct pcib_window *w, struct resource **res,
254 struct resource **newarray;
257 newarray = malloc(sizeof(struct resource *) * (w->count + count),
260 bcopy(w->res, newarray, sizeof(struct resource *) * w->count);
261 bcopy(res, newarray + w->count, sizeof(struct resource *) * count);
262 free(w->res, M_DEVBUF);
266 for (i = 0; i < count; i++) {
267 error = rman_manage_region(&w->rman, rman_get_start(res[i]),
268 rman_get_end(res[i]));
270 panic("Failed to add resource to rman");
274 typedef void (nonisa_callback)(u_long start, u_long end, void *arg);
277 pcib_walk_nonisa_ranges(u_long start, u_long end, nonisa_callback *cb,
283 * If start is within an ISA alias range, move up to the start
284 * of the next non-alias range. As a special case, addresses
285 * in the range 0x000 - 0x0ff should also be skipped since
286 * those are used for various system I/O devices in ISA
289 if (start <= 65535) {
290 if (start < 0x100 || (start & 0x300) != 0) {
296 /* ISA aliases are only in the lower 64KB of I/O space. */
297 while (start <= MIN(end, 65535)) {
298 next_end = MIN(start | 0xff, end);
299 cb(start, next_end, arg);
308 count_ranges(u_long start, u_long end, void *arg)
317 struct resource **res;
318 struct pcib_softc *sc;
323 alloc_ranges(u_long start, u_long end, void *arg)
325 struct alloc_state *as;
326 struct pcib_window *w;
336 device_printf(as->sc->dev,
337 "allocating non-ISA range %#lx-%#lx\n", start, end);
338 as->res[as->count] = bus_alloc_resource(as->sc->dev, SYS_RES_IOPORT,
339 &rid, start, end, end - start + 1, 0);
340 if (as->res[as->count] == NULL)
347 pcib_alloc_nonisa_ranges(struct pcib_softc *sc, u_long start, u_long end)
349 struct alloc_state as;
352 /* First, see how many ranges we need. */
354 pcib_walk_nonisa_ranges(start, end, count_ranges, &new_count);
356 /* Second, allocate the ranges. */
357 as.res = malloc(sizeof(struct resource *) * new_count, M_DEVBUF,
362 pcib_walk_nonisa_ranges(start, end, alloc_ranges, &as);
364 for (i = 0; i < as.count; i++)
365 bus_release_resource(sc->dev, SYS_RES_IOPORT,
366 sc->io.reg, as.res[i]);
367 free(as.res, M_DEVBUF);
370 KASSERT(as.count == new_count, ("%s: count mismatch", __func__));
372 /* Third, add the ranges to the window. */
373 pcib_add_window_resources(&sc->io, as.res, as.count);
374 free(as.res, M_DEVBUF);
379 pcib_alloc_window(struct pcib_softc *sc, struct pcib_window *w, int type,
380 int flags, pci_addr_t max_address)
382 struct resource *res;
386 if (max_address != (u_long)max_address)
388 w->rman.rm_start = 0;
389 w->rman.rm_end = max_address;
390 w->rman.rm_type = RMAN_ARRAY;
391 snprintf(buf, sizeof(buf), "%s %s window",
392 device_get_nameunit(sc->dev), w->name);
393 w->rman.rm_descr = strdup(buf, M_DEVBUF);
394 error = rman_init(&w->rman);
396 panic("Failed to initialize %s %s rman",
397 device_get_nameunit(sc->dev), w->name);
399 if (!pcib_is_window_open(w))
402 if (w->base > max_address || w->limit > max_address) {
403 device_printf(sc->dev,
404 "initial %s window has too many bits, ignoring\n", w->name);
407 if (type == SYS_RES_IOPORT && sc->bridgectl & PCIB_BCR_ISA_ENABLE)
408 (void)pcib_alloc_nonisa_ranges(sc, w->base, w->limit);
411 res = bus_alloc_resource(sc->dev, type, &rid, w->base, w->limit,
412 w->limit - w->base + 1, flags);
414 pcib_add_window_resources(w, &res, 1);
416 if (w->res == NULL) {
417 device_printf(sc->dev,
418 "failed to allocate initial %s window: %#jx-%#jx\n",
419 w->name, (uintmax_t)w->base, (uintmax_t)w->limit);
420 w->base = max_address;
422 pcib_write_windows(sc, w->mask);
425 pcib_activate_window(sc, type);
429 * Initialize I/O windows.
432 pcib_probe_windows(struct pcib_softc *sc)
440 if (pci_clear_pcib) {
441 pci_write_config(dev, PCIR_IOBASEL_1, 0xff, 1);
442 pci_write_config(dev, PCIR_IOBASEH_1, 0xffff, 2);
443 pci_write_config(dev, PCIR_IOLIMITL_1, 0, 1);
444 pci_write_config(dev, PCIR_IOLIMITH_1, 0, 2);
445 pci_write_config(dev, PCIR_MEMBASE_1, 0xffff, 2);
446 pci_write_config(dev, PCIR_MEMLIMIT_1, 0, 2);
447 pci_write_config(dev, PCIR_PMBASEL_1, 0xffff, 2);
448 pci_write_config(dev, PCIR_PMBASEH_1, 0xffffffff, 4);
449 pci_write_config(dev, PCIR_PMLIMITL_1, 0, 2);
450 pci_write_config(dev, PCIR_PMLIMITH_1, 0, 4);
453 /* Determine if the I/O port window is implemented. */
454 val = pci_read_config(dev, PCIR_IOBASEL_1, 1);
457 * If 'val' is zero, then only 16-bits of I/O space
460 pci_write_config(dev, PCIR_IOBASEL_1, 0xff, 1);
461 if (pci_read_config(dev, PCIR_IOBASEL_1, 1) != 0) {
463 pci_write_config(dev, PCIR_IOBASEL_1, 0, 1);
468 /* Read the existing I/O port window. */
470 sc->io.reg = PCIR_IOBASEL_1;
472 sc->io.mask = WIN_IO;
473 sc->io.name = "I/O port";
474 if ((val & PCIM_BRIO_MASK) == PCIM_BRIO_32) {
475 sc->io.base = PCI_PPBIOBASE(
476 pci_read_config(dev, PCIR_IOBASEH_1, 2), val);
477 sc->io.limit = PCI_PPBIOLIMIT(
478 pci_read_config(dev, PCIR_IOLIMITH_1, 2),
479 pci_read_config(dev, PCIR_IOLIMITL_1, 1));
482 sc->io.base = PCI_PPBIOBASE(0, val);
483 sc->io.limit = PCI_PPBIOLIMIT(0,
484 pci_read_config(dev, PCIR_IOLIMITL_1, 1));
487 pcib_alloc_window(sc, &sc->io, SYS_RES_IOPORT, 0, max);
490 /* Read the existing memory window. */
492 sc->mem.reg = PCIR_MEMBASE_1;
494 sc->mem.mask = WIN_MEM;
495 sc->mem.name = "memory";
496 sc->mem.base = PCI_PPBMEMBASE(0,
497 pci_read_config(dev, PCIR_MEMBASE_1, 2));
498 sc->mem.limit = PCI_PPBMEMLIMIT(0,
499 pci_read_config(dev, PCIR_MEMLIMIT_1, 2));
500 pcib_alloc_window(sc, &sc->mem, SYS_RES_MEMORY, 0, 0xffffffff);
502 /* Determine if the prefetchable memory window is implemented. */
503 val = pci_read_config(dev, PCIR_PMBASEL_1, 2);
506 * If 'val' is zero, then only 32-bits of memory space
509 pci_write_config(dev, PCIR_PMBASEL_1, 0xffff, 2);
510 if (pci_read_config(dev, PCIR_PMBASEL_1, 2) != 0) {
512 pci_write_config(dev, PCIR_PMBASEL_1, 0, 2);
517 /* Read the existing prefetchable memory window. */
518 if (sc->pmem.valid) {
519 sc->pmem.reg = PCIR_PMBASEL_1;
521 sc->pmem.mask = WIN_PMEM;
522 sc->pmem.name = "prefetch";
523 if ((val & PCIM_BRPM_MASK) == PCIM_BRPM_64) {
524 sc->pmem.base = PCI_PPBMEMBASE(
525 pci_read_config(dev, PCIR_PMBASEH_1, 4), val);
526 sc->pmem.limit = PCI_PPBMEMLIMIT(
527 pci_read_config(dev, PCIR_PMLIMITH_1, 4),
528 pci_read_config(dev, PCIR_PMLIMITL_1, 2));
529 max = 0xffffffffffffffff;
531 sc->pmem.base = PCI_PPBMEMBASE(0, val);
532 sc->pmem.limit = PCI_PPBMEMLIMIT(0,
533 pci_read_config(dev, PCIR_PMLIMITL_1, 2));
536 pcib_alloc_window(sc, &sc->pmem, SYS_RES_MEMORY,
537 RF_PREFETCHABLE, max);
543 * Allocate a suitable secondary bus for this bridge if needed and
544 * initialize the resource manager for the secondary bus range. Note
545 * that the minimum count is a desired value and this may allocate a
549 pcib_setup_secbus(device_t dev, struct pcib_secbus *bus, int min_count)
554 switch (pci_read_config(dev, PCIR_HDRTYPE, 1) & PCIM_HDRTYPE) {
555 case PCIM_HDRTYPE_BRIDGE:
556 bus->sub_reg = PCIR_SUBBUS_1;
558 case PCIM_HDRTYPE_CARDBUS:
559 bus->sub_reg = PCIR_SUBBUS_2;
562 panic("not a PCI bridge");
565 bus->rman.rm_start = 0;
566 bus->rman.rm_end = PCI_BUSMAX;
567 bus->rman.rm_type = RMAN_ARRAY;
568 snprintf(buf, sizeof(buf), "%s bus numbers", device_get_nameunit(dev));
569 bus->rman.rm_descr = strdup(buf, M_DEVBUF);
570 error = rman_init(&bus->rman);
572 panic("Failed to initialize %s bus number rman",
573 device_get_nameunit(dev));
576 * Allocate a bus range. This will return an existing bus range
577 * if one exists, or a new bus range if one does not.
580 bus->res = bus_alloc_resource(dev, PCI_RES_BUS, &rid, 0ul, ~0ul,
582 if (bus->res == NULL) {
584 * Fall back to just allocating a range of a single bus
587 bus->res = bus_alloc_resource(dev, PCI_RES_BUS, &rid, 0ul, ~0ul,
589 } else if (rman_get_size(bus->res) < min_count)
591 * Attempt to grow the existing range to satisfy the
592 * minimum desired count.
594 (void)bus_adjust_resource(dev, PCI_RES_BUS, bus->res,
595 rman_get_start(bus->res), rman_get_start(bus->res) +
599 * Add the initial resource to the rman.
601 if (bus->res != NULL) {
602 error = rman_manage_region(&bus->rman, rman_get_start(bus->res),
603 rman_get_end(bus->res));
605 panic("Failed to add resource to rman");
606 bus->sec = rman_get_start(bus->res);
607 bus->sub = rman_get_end(bus->res);
611 static struct resource *
612 pcib_suballoc_bus(struct pcib_secbus *bus, device_t child, int *rid,
613 u_long start, u_long end, u_long count, u_int flags)
615 struct resource *res;
617 res = rman_reserve_resource(&bus->rman, start, end, count, flags,
623 device_printf(bus->dev,
624 "allocated bus range (%lu-%lu) for rid %d of %s\n",
625 rman_get_start(res), rman_get_end(res), *rid,
626 pcib_child_name(child));
627 rman_set_rid(res, *rid);
632 * Attempt to grow the secondary bus range. This is much simpler than
633 * for I/O windows as the range can only be grown by increasing
637 pcib_grow_subbus(struct pcib_secbus *bus, u_long new_end)
642 old_end = rman_get_end(bus->res);
643 KASSERT(new_end > old_end, ("attempt to shrink subbus"));
644 error = bus_adjust_resource(bus->dev, PCI_RES_BUS, bus->res,
645 rman_get_start(bus->res), new_end);
649 device_printf(bus->dev, "grew bus range to %lu-%lu\n",
650 rman_get_start(bus->res), rman_get_end(bus->res));
651 error = rman_manage_region(&bus->rman, old_end + 1,
652 rman_get_end(bus->res));
654 panic("Failed to add resource to rman");
655 bus->sub = rman_get_end(bus->res);
656 pci_write_config(bus->dev, bus->sub_reg, bus->sub, 1);
661 pcib_alloc_subbus(struct pcib_secbus *bus, device_t child, int *rid,
662 u_long start, u_long end, u_long count, u_int flags)
664 struct resource *res;
665 u_long start_free, end_free, new_end;
668 * First, see if the request can be satisified by the existing
671 res = pcib_suballoc_bus(bus, child, rid, start, end, count, flags);
676 * Figure out a range to grow the bus range. First, find the
677 * first bus number after the last allocated bus in the rman and
678 * enforce that as a minimum starting point for the range.
680 if (rman_last_free_region(&bus->rman, &start_free, &end_free) != 0 ||
681 end_free != bus->sub)
682 start_free = bus->sub + 1;
683 if (start_free < start)
685 new_end = start_free + count - 1;
688 * See if this new range would satisfy the request if it
694 /* Finally, attempt to grow the existing resource. */
696 device_printf(bus->dev,
697 "attempting to grow bus range for %lu buses\n", count);
698 printf("\tback candidate range: %lu-%lu\n", start_free,
701 if (pcib_grow_subbus(bus, new_end) == 0)
702 return (pcib_suballoc_bus(bus, child, rid, start, end, count,
711 * Is the prefetch window open (eg, can we allocate memory in it?)
714 pcib_is_prefetch_open(struct pcib_softc *sc)
716 return (sc->pmembase > 0 && sc->pmembase < sc->pmemlimit);
720 * Is the nonprefetch window open (eg, can we allocate memory in it?)
723 pcib_is_nonprefetch_open(struct pcib_softc *sc)
725 return (sc->membase > 0 && sc->membase < sc->memlimit);
729 * Is the io window open (eg, can we allocate ports in it?)
732 pcib_is_io_open(struct pcib_softc *sc)
734 return (sc->iobase > 0 && sc->iobase < sc->iolimit);
738 * Get current I/O decode.
741 pcib_get_io_decode(struct pcib_softc *sc)
748 iolow = pci_read_config(dev, PCIR_IOBASEL_1, 1);
749 if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32)
750 sc->iobase = PCI_PPBIOBASE(
751 pci_read_config(dev, PCIR_IOBASEH_1, 2), iolow);
753 sc->iobase = PCI_PPBIOBASE(0, iolow);
755 iolow = pci_read_config(dev, PCIR_IOLIMITL_1, 1);
756 if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32)
757 sc->iolimit = PCI_PPBIOLIMIT(
758 pci_read_config(dev, PCIR_IOLIMITH_1, 2), iolow);
760 sc->iolimit = PCI_PPBIOLIMIT(0, iolow);
764 * Get current memory decode.
767 pcib_get_mem_decode(struct pcib_softc *sc)
774 sc->membase = PCI_PPBMEMBASE(0,
775 pci_read_config(dev, PCIR_MEMBASE_1, 2));
776 sc->memlimit = PCI_PPBMEMLIMIT(0,
777 pci_read_config(dev, PCIR_MEMLIMIT_1, 2));
779 pmemlow = pci_read_config(dev, PCIR_PMBASEL_1, 2);
780 if ((pmemlow & PCIM_BRPM_MASK) == PCIM_BRPM_64)
781 sc->pmembase = PCI_PPBMEMBASE(
782 pci_read_config(dev, PCIR_PMBASEH_1, 4), pmemlow);
784 sc->pmembase = PCI_PPBMEMBASE(0, pmemlow);
786 pmemlow = pci_read_config(dev, PCIR_PMLIMITL_1, 2);
787 if ((pmemlow & PCIM_BRPM_MASK) == PCIM_BRPM_64)
788 sc->pmemlimit = PCI_PPBMEMLIMIT(
789 pci_read_config(dev, PCIR_PMLIMITH_1, 4), pmemlow);
791 sc->pmemlimit = PCI_PPBMEMLIMIT(0, pmemlow);
795 * Restore previous I/O decode.
798 pcib_set_io_decode(struct pcib_softc *sc)
805 iohi = sc->iobase >> 16;
807 pci_write_config(dev, PCIR_IOBASEH_1, iohi, 2);
808 pci_write_config(dev, PCIR_IOBASEL_1, sc->iobase >> 8, 1);
810 iohi = sc->iolimit >> 16;
812 pci_write_config(dev, PCIR_IOLIMITH_1, iohi, 2);
813 pci_write_config(dev, PCIR_IOLIMITL_1, sc->iolimit >> 8, 1);
817 * Restore previous memory decode.
820 pcib_set_mem_decode(struct pcib_softc *sc)
827 pci_write_config(dev, PCIR_MEMBASE_1, sc->membase >> 16, 2);
828 pci_write_config(dev, PCIR_MEMLIMIT_1, sc->memlimit >> 16, 2);
830 pmemhi = sc->pmembase >> 32;
832 pci_write_config(dev, PCIR_PMBASEH_1, pmemhi, 4);
833 pci_write_config(dev, PCIR_PMBASEL_1, sc->pmembase >> 16, 2);
835 pmemhi = sc->pmemlimit >> 32;
837 pci_write_config(dev, PCIR_PMLIMITH_1, pmemhi, 4);
838 pci_write_config(dev, PCIR_PMLIMITL_1, sc->pmemlimit >> 16, 2);
843 * Get current bridge configuration.
846 pcib_cfg_save(struct pcib_softc *sc)
852 sc->command = pci_read_config(dev, PCIR_COMMAND, 2);
853 sc->pribus = pci_read_config(dev, PCIR_PRIBUS_1, 1);
854 sc->bus.sec = pci_read_config(dev, PCIR_SECBUS_1, 1);
855 sc->bus.sub = pci_read_config(dev, PCIR_SUBBUS_1, 1);
856 sc->bridgectl = pci_read_config(dev, PCIR_BRIDGECTL_1, 2);
857 sc->seclat = pci_read_config(dev, PCIR_SECLAT_1, 1);
859 if (sc->command & PCIM_CMD_PORTEN)
860 pcib_get_io_decode(sc);
861 if (sc->command & PCIM_CMD_MEMEN)
862 pcib_get_mem_decode(sc);
867 * Restore previous bridge configuration.
870 pcib_cfg_restore(struct pcib_softc *sc)
876 pci_write_config(dev, PCIR_COMMAND, sc->command, 2);
877 pci_write_config(dev, PCIR_PRIBUS_1, sc->pribus, 1);
878 pci_write_config(dev, PCIR_SECBUS_1, sc->bus.sec, 1);
879 pci_write_config(dev, PCIR_SUBBUS_1, sc->bus.sub, 1);
880 pci_write_config(dev, PCIR_BRIDGECTL_1, sc->bridgectl, 2);
881 pci_write_config(dev, PCIR_SECLAT_1, sc->seclat, 1);
883 pcib_write_windows(sc, WIN_IO | WIN_MEM | WIN_PMEM);
885 if (sc->command & PCIM_CMD_PORTEN)
886 pcib_set_io_decode(sc);
887 if (sc->command & PCIM_CMD_MEMEN)
888 pcib_set_mem_decode(sc);
893 * Generic device interface
896 pcib_probe(device_t dev)
898 if ((pci_get_class(dev) == PCIC_BRIDGE) &&
899 (pci_get_subclass(dev) == PCIS_BRIDGE_PCI)) {
900 device_set_desc(dev, "PCI-PCI bridge");
907 pcib_attach_common(device_t dev)
909 struct pcib_softc *sc;
910 struct sysctl_ctx_list *sctx;
911 struct sysctl_oid *soid;
914 sc = device_get_softc(dev);
918 * Get current bridge configuration.
920 sc->domain = pci_get_domain(dev);
921 sc->secstat = pci_read_config(dev, PCIR_SECSTAT_1, 2);
925 * The primary bus register should always be the bus of the
928 sc->pribus = pci_get_bus(dev);
929 pci_write_config(dev, PCIR_PRIBUS_1, sc->pribus, 1);
932 * Setup sysctl reporting nodes
934 sctx = device_get_sysctl_ctx(dev);
935 soid = device_get_sysctl_tree(dev);
936 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "domain",
937 CTLFLAG_RD, &sc->domain, 0, "Domain number");
938 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "pribus",
939 CTLFLAG_RD, &sc->pribus, 0, "Primary bus number");
940 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "secbus",
941 CTLFLAG_RD, &sc->bus.sec, 0, "Secondary bus number");
942 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "subbus",
943 CTLFLAG_RD, &sc->bus.sub, 0, "Subordinate bus number");
948 switch (pci_get_devid(dev)) {
949 #if !(defined(NEW_PCIB) && defined(PCI_RES_BUS))
950 case 0x12258086: /* Intel 82454KX/GX (Orion) */
954 supbus = pci_read_config(dev, 0x41, 1);
955 if (supbus != 0xff) {
956 sc->bus.sec = supbus + 1;
957 sc->bus.sub = supbus + 1;
964 * The i82380FB mobile docking controller is a PCI-PCI bridge,
965 * and it is a subtractive bridge. However, the ProgIf is wrong
966 * so the normal setting of PCIB_SUBTRACTIVE bit doesn't
967 * happen. There's also a Toshiba bridge that behaves this
970 case 0x124b8086: /* Intel 82380FB Mobile */
971 case 0x060513d7: /* Toshiba ???? */
972 sc->flags |= PCIB_SUBTRACTIVE;
975 #if !(defined(NEW_PCIB) && defined(PCI_RES_BUS))
976 /* Compaq R3000 BIOS sets wrong subordinate bus number. */
981 if ((cp = getenv("smbios.planar.maker")) == NULL)
983 if (strncmp(cp, "Compal", 6) != 0) {
988 if ((cp = getenv("smbios.planar.product")) == NULL)
990 if (strncmp(cp, "08A0", 4) != 0) {
995 if (sc->bus.sub < 0xa) {
996 pci_write_config(dev, PCIR_SUBBUS_1, 0xa, 1);
997 sc->bus.sub = pci_read_config(dev, PCIR_SUBBUS_1, 1);
1004 if (pci_msi_device_blacklisted(dev))
1005 sc->flags |= PCIB_DISABLE_MSI;
1007 if (pci_msix_device_blacklisted(dev))
1008 sc->flags |= PCIB_DISABLE_MSIX;
1011 * Intel 815, 845 and other chipsets say they are PCI-PCI bridges,
1012 * but have a ProgIF of 0x80. The 82801 family (AA, AB, BAM/CAM,
1013 * BA/CA/DB and E) PCI bridges are HUB-PCI bridges, in Intelese.
1014 * This means they act as if they were subtractively decoding
1015 * bridges and pass all transactions. Mark them and real ProgIf 1
1016 * parts as subtractive.
1018 if ((pci_get_devid(dev) & 0xff00ffff) == 0x24008086 ||
1019 pci_read_config(dev, PCIR_PROGIF, 1) == PCIP_BRIDGE_PCI_SUBTRACTIVE)
1020 sc->flags |= PCIB_SUBTRACTIVE;
1024 pcib_setup_secbus(dev, &sc->bus, 1);
1026 pcib_probe_windows(sc);
1029 device_printf(dev, " domain %d\n", sc->domain);
1030 device_printf(dev, " secondary bus %d\n", sc->bus.sec);
1031 device_printf(dev, " subordinate bus %d\n", sc->bus.sub);
1033 if (pcib_is_window_open(&sc->io))
1034 device_printf(dev, " I/O decode 0x%jx-0x%jx\n",
1035 (uintmax_t)sc->io.base, (uintmax_t)sc->io.limit);
1036 if (pcib_is_window_open(&sc->mem))
1037 device_printf(dev, " memory decode 0x%jx-0x%jx\n",
1038 (uintmax_t)sc->mem.base, (uintmax_t)sc->mem.limit);
1039 if (pcib_is_window_open(&sc->pmem))
1040 device_printf(dev, " prefetched decode 0x%jx-0x%jx\n",
1041 (uintmax_t)sc->pmem.base, (uintmax_t)sc->pmem.limit);
1043 if (pcib_is_io_open(sc))
1044 device_printf(dev, " I/O decode 0x%x-0x%x\n",
1045 sc->iobase, sc->iolimit);
1046 if (pcib_is_nonprefetch_open(sc))
1047 device_printf(dev, " memory decode 0x%jx-0x%jx\n",
1048 (uintmax_t)sc->membase, (uintmax_t)sc->memlimit);
1049 if (pcib_is_prefetch_open(sc))
1050 device_printf(dev, " prefetched decode 0x%jx-0x%jx\n",
1051 (uintmax_t)sc->pmembase, (uintmax_t)sc->pmemlimit);
1053 if (sc->bridgectl & (PCIB_BCR_ISA_ENABLE | PCIB_BCR_VGA_ENABLE) ||
1054 sc->flags & PCIB_SUBTRACTIVE) {
1055 device_printf(dev, " special decode ");
1057 if (sc->bridgectl & PCIB_BCR_ISA_ENABLE) {
1061 if (sc->bridgectl & PCIB_BCR_VGA_ENABLE) {
1062 printf("%sVGA", comma ? ", " : "");
1065 if (sc->flags & PCIB_SUBTRACTIVE)
1066 printf("%ssubtractive", comma ? ", " : "");
1072 * Always enable busmastering on bridges so that transactions
1073 * initiated on the secondary bus are passed through to the
1076 pci_enable_busmaster(dev);
1080 pcib_attach(device_t dev)
1082 struct pcib_softc *sc;
1085 pcib_attach_common(dev);
1086 sc = device_get_softc(dev);
1087 if (sc->bus.sec != 0) {
1088 child = device_add_child(dev, "pci", sc->bus.sec);
1090 return(bus_generic_attach(dev));
1093 /* no secondary bus; we should have fixed this */
1098 pcib_suspend(device_t dev)
1101 pcib_cfg_save(device_get_softc(dev));
1102 return (bus_generic_suspend(dev));
1106 pcib_resume(device_t dev)
1109 pcib_cfg_restore(device_get_softc(dev));
1110 return (bus_generic_resume(dev));
1114 pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
1116 struct pcib_softc *sc = device_get_softc(dev);
1119 case PCIB_IVAR_DOMAIN:
1120 *result = sc->domain;
1123 *result = sc->bus.sec;
1130 pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
1134 case PCIB_IVAR_DOMAIN:
1144 * Attempt to allocate a resource from the existing resources assigned
1147 static struct resource *
1148 pcib_suballoc_resource(struct pcib_softc *sc, struct pcib_window *w,
1149 device_t child, int type, int *rid, u_long start, u_long end, u_long count,
1152 struct resource *res;
1154 if (!pcib_is_window_open(w))
1157 res = rman_reserve_resource(&w->rman, start, end, count,
1158 flags & ~RF_ACTIVE, child);
1163 device_printf(sc->dev,
1164 "allocated %s range (%#lx-%#lx) for rid %x of %s\n",
1165 w->name, rman_get_start(res), rman_get_end(res), *rid,
1166 pcib_child_name(child));
1167 rman_set_rid(res, *rid);
1170 * If the resource should be active, pass that request up the
1171 * tree. This assumes the parent drivers can handle
1172 * activating sub-allocated resources.
1174 if (flags & RF_ACTIVE) {
1175 if (bus_activate_resource(child, type, *rid, res) != 0) {
1176 rman_release_resource(res);
1184 /* Allocate a fresh resource range for an unconfigured window. */
1186 pcib_alloc_new_window(struct pcib_softc *sc, struct pcib_window *w, int type,
1187 u_long start, u_long end, u_long count, u_int flags)
1189 struct resource *res;
1190 u_long base, limit, wmask;
1194 * If this is an I/O window on a bridge with ISA enable set
1195 * and the start address is below 64k, then try to allocate an
1196 * initial window of 0x1000 bytes long starting at address
1197 * 0xf000 and walking down. Note that if the original request
1198 * was larger than the non-aliased range size of 0x100 our
1199 * caller would have raised the start address up to 64k
1202 if (type == SYS_RES_IOPORT && sc->bridgectl & PCIB_BCR_ISA_ENABLE &&
1204 for (base = 0xf000; (long)base >= 0; base -= 0x1000) {
1205 limit = base + 0xfff;
1208 * Skip ranges that wouldn't work for the
1209 * original request. Note that the actual
1210 * window that overlaps are the non-alias
1211 * ranges within [base, limit], so this isn't
1212 * quite a simple comparison.
1214 if (start + count > limit - 0x400)
1218 * The first open region for the window at
1221 if (end - count + 1 < 0x400)
1224 if (end - count + 1 < base)
1228 if (pcib_alloc_nonisa_ranges(sc, base, limit) == 0) {
1237 wmask = (1ul << w->step) - 1;
1238 if (RF_ALIGNMENT(flags) < w->step) {
1239 flags &= ~RF_ALIGNMENT_MASK;
1240 flags |= RF_ALIGNMENT_LOG2(w->step);
1244 count = roundup2(count, 1ul << w->step);
1246 res = bus_alloc_resource(sc->dev, type, &rid, start, end, count,
1247 flags & ~RF_ACTIVE);
1250 pcib_add_window_resources(w, &res, 1);
1251 pcib_activate_window(sc, type);
1252 w->base = rman_get_start(res);
1253 w->limit = rman_get_end(res);
1257 /* Try to expand an existing window to the requested base and limit. */
1259 pcib_expand_window(struct pcib_softc *sc, struct pcib_window *w, int type,
1260 u_long base, u_long limit)
1262 struct resource *res;
1263 int error, i, force_64k_base;
1265 KASSERT(base <= w->base && limit >= w->limit,
1266 ("attempting to shrink window"));
1269 * XXX: pcib_grow_window() doesn't try to do this anyway and
1270 * the error handling for all the edge cases would be tedious.
1272 KASSERT(limit == w->limit || base == w->base,
1273 ("attempting to grow both ends of a window"));
1276 * Yet more special handling for requests to expand an I/O
1277 * window behind an ISA-enabled bridge. Since I/O windows
1278 * have to grow in 0x1000 increments and the end of the 0xffff
1279 * range is an alias, growing a window below 64k will always
1280 * result in allocating new resources and never adjusting an
1281 * existing resource.
1283 if (type == SYS_RES_IOPORT && sc->bridgectl & PCIB_BCR_ISA_ENABLE &&
1284 (limit <= 65535 || (base <= 65535 && base != w->base))) {
1285 KASSERT(limit == w->limit || limit <= 65535,
1286 ("attempting to grow both ends across 64k ISA alias"));
1288 if (base != w->base)
1289 error = pcib_alloc_nonisa_ranges(sc, base, w->base - 1);
1291 error = pcib_alloc_nonisa_ranges(sc, w->limit + 1,
1301 * Find the existing resource to adjust. Usually there is only one,
1302 * but for an ISA-enabled bridge we might be growing the I/O window
1303 * above 64k and need to find the existing resource that maps all
1304 * of the area above 64k.
1306 for (i = 0; i < w->count; i++) {
1307 if (rman_get_end(w->res[i]) == w->limit)
1310 KASSERT(i != w->count, ("did not find existing resource"));
1314 * Usually the resource we found should match the window's
1315 * existing range. The one exception is the ISA-enabled case
1316 * mentioned above in which case the resource should start at
1319 if (type == SYS_RES_IOPORT && sc->bridgectl & PCIB_BCR_ISA_ENABLE &&
1321 KASSERT(rman_get_start(res) == 65536,
1322 ("existing resource mismatch"));
1325 KASSERT(w->base == rman_get_start(res),
1326 ("existing resource mismatch"));
1330 error = bus_adjust_resource(sc->dev, type, res, force_64k_base ?
1331 rman_get_start(res) : base, limit);
1335 /* Add the newly allocated region to the resource manager. */
1336 if (w->base != base) {
1337 error = rman_manage_region(&w->rman, base, w->base - 1);
1340 error = rman_manage_region(&w->rman, w->limit + 1, limit);
1345 device_printf(sc->dev,
1346 "failed to expand %s resource manager\n", w->name);
1347 (void)bus_adjust_resource(sc->dev, type, res, force_64k_base ?
1348 rman_get_start(res) : w->base, w->limit);
1354 * Attempt to grow a window to make room for a given resource request.
1357 pcib_grow_window(struct pcib_softc *sc, struct pcib_window *w, int type,
1358 u_long start, u_long end, u_long count, u_int flags)
1360 u_long align, start_free, end_free, front, back, wmask;
1364 * Clamp the desired resource range to the maximum address
1365 * this window supports. Reject impossible requests.
1367 * For I/O port requests behind a bridge with the ISA enable
1368 * bit set, force large allocations to start above 64k.
1372 if (sc->bridgectl & PCIB_BCR_ISA_ENABLE && count > 0x100 &&
1375 if (end > w->rman.rm_end)
1376 end = w->rman.rm_end;
1377 if (start + count - 1 > end || start + count < start)
1379 wmask = (1ul << w->step) - 1;
1382 * If there is no resource at all, just try to allocate enough
1383 * aligned space for this resource.
1385 if (w->res == NULL) {
1386 error = pcib_alloc_new_window(sc, w, type, start, end, count,
1390 device_printf(sc->dev,
1391 "failed to allocate initial %s window (%#lx-%#lx,%#lx)\n",
1392 w->name, start, end, count);
1396 device_printf(sc->dev,
1397 "allocated initial %s window of %#jx-%#jx\n",
1398 w->name, (uintmax_t)w->base, (uintmax_t)w->limit);
1403 * See if growing the window would help. Compute the minimum
1404 * amount of address space needed on both the front and back
1405 * ends of the existing window to satisfy the allocation.
1407 * For each end, build a candidate region adjusting for the
1408 * required alignment, etc. If there is a free region at the
1409 * edge of the window, grow from the inner edge of the free
1410 * region. Otherwise grow from the window boundary.
1412 * Growing an I/O window below 64k for a bridge with the ISA
1413 * enable bit doesn't require any special magic as the step
1414 * size of an I/O window (1k) always includes multiple
1415 * non-alias ranges when it is grown in either direction.
1417 * XXX: Special case: if w->res is completely empty and the
1418 * request size is larger than w->res, we should find the
1419 * optimal aligned buffer containing w->res and allocate that.
1422 device_printf(sc->dev,
1423 "attempting to grow %s window for (%#lx-%#lx,%#lx)\n",
1424 w->name, start, end, count);
1425 align = 1ul << RF_ALIGNMENT(flags);
1426 if (start < w->base) {
1427 if (rman_first_free_region(&w->rman, &start_free, &end_free) !=
1428 0 || start_free != w->base)
1433 /* Move end_free down until it is properly aligned. */
1434 end_free &= ~(align - 1);
1436 front = end_free - (count - 1);
1439 * The resource would now be allocated at (front,
1440 * end_free). Ensure that fits in the (start, end)
1441 * bounds. end_free is checked above. If 'front' is
1442 * ok, ensure it is properly aligned for this window.
1443 * Also check for underflow.
1445 if (front >= start && front <= end_free) {
1447 printf("\tfront candidate range: %#lx-%#lx\n",
1450 front = w->base - front;
1455 if (end > w->limit) {
1456 if (rman_last_free_region(&w->rman, &start_free, &end_free) !=
1457 0 || end_free != w->limit)
1458 start_free = w->limit + 1;
1459 if (start_free < start)
1462 /* Move start_free up until it is properly aligned. */
1463 start_free = roundup2(start_free, align);
1464 back = start_free + count - 1;
1467 * The resource would now be allocated at (start_free,
1468 * back). Ensure that fits in the (start, end)
1469 * bounds. start_free is checked above. If 'back' is
1470 * ok, ensure it is properly aligned for this window.
1471 * Also check for overflow.
1473 if (back <= end && start_free <= back) {
1475 printf("\tback candidate range: %#lx-%#lx\n",
1485 * Try to allocate the smallest needed region first.
1486 * If that fails, fall back to the other region.
1489 while (front != 0 || back != 0) {
1490 if (front != 0 && (front <= back || back == 0)) {
1491 error = pcib_expand_window(sc, w, type, w->base - front,
1497 error = pcib_expand_window(sc, w, type, w->base,
1508 device_printf(sc->dev, "grew %s window to %#jx-%#jx\n",
1509 w->name, (uintmax_t)w->base, (uintmax_t)w->limit);
1512 /* Write the new window. */
1513 KASSERT((w->base & wmask) == 0, ("start address is not aligned"));
1514 KASSERT((w->limit & wmask) == wmask, ("end address is not aligned"));
1515 pcib_write_windows(sc, w->mask);
1520 * We have to trap resource allocation requests and ensure that the bridge
1521 * is set up to, or capable of handling them.
1524 pcib_alloc_resource(device_t dev, device_t child, int type, int *rid,
1525 u_long start, u_long end, u_long count, u_int flags)
1527 struct pcib_softc *sc;
1530 sc = device_get_softc(dev);
1533 * VGA resources are decoded iff the VGA enable bit is set in
1534 * the bridge control register. VGA resources do not fall into
1535 * the resource windows and are passed up to the parent.
1537 if ((type == SYS_RES_IOPORT && pci_is_vga_ioport_range(start, end)) ||
1538 (type == SYS_RES_MEMORY && pci_is_vga_memory_range(start, end))) {
1539 if (sc->bridgectl & PCIB_BCR_VGA_ENABLE)
1540 return (bus_generic_alloc_resource(dev, child, type,
1541 rid, start, end, count, flags));
1549 return (pcib_alloc_subbus(&sc->bus, child, rid, start, end,
1552 case SYS_RES_IOPORT:
1553 if (pcib_is_isa_range(sc, start, end, count))
1555 r = pcib_suballoc_resource(sc, &sc->io, child, type, rid, start,
1557 if (r != NULL || (sc->flags & PCIB_SUBTRACTIVE) != 0)
1559 if (pcib_grow_window(sc, &sc->io, type, start, end, count,
1561 r = pcib_suballoc_resource(sc, &sc->io, child, type,
1562 rid, start, end, count, flags);
1564 case SYS_RES_MEMORY:
1566 * For prefetchable resources, prefer the prefetchable
1567 * memory window, but fall back to the regular memory
1568 * window if that fails. Try both windows before
1569 * attempting to grow a window in case the firmware
1570 * has used a range in the regular memory window to
1571 * map a prefetchable BAR.
1573 if (flags & RF_PREFETCHABLE) {
1574 r = pcib_suballoc_resource(sc, &sc->pmem, child, type,
1575 rid, start, end, count, flags);
1579 r = pcib_suballoc_resource(sc, &sc->mem, child, type, rid,
1580 start, end, count, flags);
1581 if (r != NULL || (sc->flags & PCIB_SUBTRACTIVE) != 0)
1583 if (flags & RF_PREFETCHABLE) {
1584 if (pcib_grow_window(sc, &sc->pmem, type, start, end,
1585 count, flags) == 0) {
1586 r = pcib_suballoc_resource(sc, &sc->pmem, child,
1587 type, rid, start, end, count, flags);
1592 if (pcib_grow_window(sc, &sc->mem, type, start, end, count,
1593 flags & ~RF_PREFETCHABLE) == 0)
1594 r = pcib_suballoc_resource(sc, &sc->mem, child, type,
1595 rid, start, end, count, flags);
1598 return (bus_generic_alloc_resource(dev, child, type, rid,
1599 start, end, count, flags));
1603 * If attempts to suballocate from the window fail but this is a
1604 * subtractive bridge, pass the request up the tree.
1606 if (sc->flags & PCIB_SUBTRACTIVE && r == NULL)
1607 return (bus_generic_alloc_resource(dev, child, type, rid,
1608 start, end, count, flags));
1613 pcib_adjust_resource(device_t bus, device_t child, int type, struct resource *r,
1614 u_long start, u_long end)
1616 struct pcib_softc *sc;
1618 sc = device_get_softc(bus);
1619 if (pcib_is_resource_managed(sc, type, r))
1620 return (rman_adjust_resource(r, start, end));
1621 return (bus_generic_adjust_resource(bus, child, type, r, start, end));
1625 pcib_release_resource(device_t dev, device_t child, int type, int rid,
1628 struct pcib_softc *sc;
1631 sc = device_get_softc(dev);
1632 if (pcib_is_resource_managed(sc, type, r)) {
1633 if (rman_get_flags(r) & RF_ACTIVE) {
1634 error = bus_deactivate_resource(child, type, rid, r);
1638 return (rman_release_resource(r));
1640 return (bus_generic_release_resource(dev, child, type, rid, r));
1644 * We have to trap resource allocation requests and ensure that the bridge
1645 * is set up to, or capable of handling them.
1648 pcib_alloc_resource(device_t dev, device_t child, int type, int *rid,
1649 u_long start, u_long end, u_long count, u_int flags)
1651 struct pcib_softc *sc = device_get_softc(dev);
1652 const char *name, *suffix;
1656 * Fail the allocation for this range if it's not supported.
1658 name = device_get_nameunit(child);
1665 case SYS_RES_IOPORT:
1667 if (!pcib_is_io_open(sc))
1669 ok = (start >= sc->iobase && end <= sc->iolimit);
1672 * Make sure we allow access to VGA I/O addresses when the
1673 * bridge has the "VGA Enable" bit set.
1675 if (!ok && pci_is_vga_ioport_range(start, end))
1676 ok = (sc->bridgectl & PCIB_BCR_VGA_ENABLE) ? 1 : 0;
1678 if ((sc->flags & PCIB_SUBTRACTIVE) == 0) {
1680 if (start < sc->iobase)
1682 if (end > sc->iolimit)
1691 * If we overlap with the subtractive range, then
1692 * pick the upper range to use.
1694 if (start < sc->iolimit && end > sc->iobase)
1695 start = sc->iolimit + 1;
1699 device_printf(dev, "ioport: end (%lx) < start (%lx)\n",
1706 device_printf(dev, "%s%srequested unsupported I/O "
1707 "range 0x%lx-0x%lx (decoding 0x%x-0x%x)\n",
1708 name, suffix, start, end, sc->iobase, sc->iolimit);
1713 "%s%srequested I/O range 0x%lx-0x%lx: in range\n",
1714 name, suffix, start, end);
1717 case SYS_RES_MEMORY:
1719 if (pcib_is_nonprefetch_open(sc))
1720 ok = ok || (start >= sc->membase && end <= sc->memlimit);
1721 if (pcib_is_prefetch_open(sc))
1722 ok = ok || (start >= sc->pmembase && end <= sc->pmemlimit);
1725 * Make sure we allow access to VGA memory addresses when the
1726 * bridge has the "VGA Enable" bit set.
1728 if (!ok && pci_is_vga_memory_range(start, end))
1729 ok = (sc->bridgectl & PCIB_BCR_VGA_ENABLE) ? 1 : 0;
1731 if ((sc->flags & PCIB_SUBTRACTIVE) == 0) {
1734 if (flags & RF_PREFETCHABLE) {
1735 if (pcib_is_prefetch_open(sc)) {
1736 if (start < sc->pmembase)
1737 start = sc->pmembase;
1738 if (end > sc->pmemlimit)
1739 end = sc->pmemlimit;
1743 } else { /* non-prefetchable */
1744 if (pcib_is_nonprefetch_open(sc)) {
1745 if (start < sc->membase)
1746 start = sc->membase;
1747 if (end > sc->memlimit)
1755 ok = 1; /* subtractive bridge: always ok */
1757 if (pcib_is_nonprefetch_open(sc)) {
1758 if (start < sc->memlimit && end > sc->membase)
1759 start = sc->memlimit + 1;
1761 if (pcib_is_prefetch_open(sc)) {
1762 if (start < sc->pmemlimit && end > sc->pmembase)
1763 start = sc->pmemlimit + 1;
1768 device_printf(dev, "memory: end (%lx) < start (%lx)\n",
1774 if (!ok && bootverbose)
1776 "%s%srequested unsupported memory range %#lx-%#lx "
1777 "(decoding %#jx-%#jx, %#jx-%#jx)\n",
1778 name, suffix, start, end,
1779 (uintmax_t)sc->membase, (uintmax_t)sc->memlimit,
1780 (uintmax_t)sc->pmembase, (uintmax_t)sc->pmemlimit);
1784 device_printf(dev,"%s%srequested memory range "
1785 "0x%lx-0x%lx: good\n",
1786 name, suffix, start, end);
1793 * Bridge is OK decoding this resource, so pass it up.
1795 return (bus_generic_alloc_resource(dev, child, type, rid, start, end,
1801 * If ARI is enabled on this downstream port, translate the function number
1802 * to the non-ARI slot/function. The downstream port will convert it back in
1803 * hardware. If ARI is not enabled slot and func are not modified.
1805 static __inline void
1806 pcib_xlate_ari(device_t pcib, int bus, int *slot, int *func)
1808 struct pcib_softc *sc;
1811 sc = device_get_softc(pcib);
1814 if (sc->flags & PCIB_ENABLE_ARI) {
1816 ("Non-zero slot number with ARI enabled!"));
1817 *slot = PCIE_ARI_SLOT(ari_func);
1818 *func = PCIE_ARI_FUNC(ari_func);
1824 pcib_enable_ari(struct pcib_softc *sc, uint32_t pcie_pos)
1828 ctl2 = pci_read_config(sc->dev, pcie_pos + PCIER_DEVICE_CTL2, 4);
1829 ctl2 |= PCIEM_CTL2_ARI;
1830 pci_write_config(sc->dev, pcie_pos + PCIER_DEVICE_CTL2, ctl2, 4);
1832 sc->flags |= PCIB_ENABLE_ARI;
1839 pcib_maxslots(device_t dev)
1841 return (PCI_SLOTMAX);
1845 pcib_ari_maxslots(device_t dev)
1847 struct pcib_softc *sc;
1849 sc = device_get_softc(dev);
1851 if (sc->flags & PCIB_ENABLE_ARI)
1852 return (PCIE_ARI_SLOTMAX);
1854 return (PCI_SLOTMAX);
1858 pcib_ari_maxfuncs(device_t dev)
1860 struct pcib_softc *sc;
1862 sc = device_get_softc(dev);
1864 if (sc->flags & PCIB_ENABLE_ARI)
1865 return (PCIE_ARI_FUNCMAX);
1867 return (PCI_FUNCMAX);
1871 * Since we are a child of a PCI bus, its parent must support the pcib interface.
1874 pcib_read_config(device_t dev, u_int b, u_int s, u_int f, u_int reg, int width)
1877 pcib_xlate_ari(dev, b, &s, &f);
1878 return(PCIB_READ_CONFIG(device_get_parent(device_get_parent(dev)), b, s,
1883 pcib_write_config(device_t dev, u_int b, u_int s, u_int f, u_int reg, uint32_t val, int width)
1886 pcib_xlate_ari(dev, b, &s, &f);
1887 PCIB_WRITE_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f,
1892 * Route an interrupt across a PCI bridge.
1895 pcib_route_interrupt(device_t pcib, device_t dev, int pin)
1903 * The PCI standard defines a swizzle of the child-side device/intpin to
1904 * the parent-side intpin as follows.
1906 * device = device on child bus
1907 * child_intpin = intpin on child bus slot (0-3)
1908 * parent_intpin = intpin on parent bus slot (0-3)
1910 * parent_intpin = (device + child_intpin) % 4
1912 parent_intpin = (pci_get_slot(dev) + (pin - 1)) % 4;
1915 * Our parent is a PCI bus. Its parent must export the pcib interface
1916 * which includes the ability to route interrupts.
1918 bus = device_get_parent(pcib);
1919 intnum = PCIB_ROUTE_INTERRUPT(device_get_parent(bus), pcib, parent_intpin + 1);
1920 if (PCI_INTERRUPT_VALID(intnum) && bootverbose) {
1921 device_printf(pcib, "slot %d INT%c is routed to irq %d\n",
1922 pci_get_slot(dev), 'A' + pin - 1, intnum);
1927 /* Pass request to alloc MSI/MSI-X messages up to the parent bridge. */
1929 pcib_alloc_msi(device_t pcib, device_t dev, int count, int maxcount, int *irqs)
1931 struct pcib_softc *sc = device_get_softc(pcib);
1934 if (sc->flags & PCIB_DISABLE_MSI)
1936 bus = device_get_parent(pcib);
1937 return (PCIB_ALLOC_MSI(device_get_parent(bus), dev, count, maxcount,
1941 /* Pass request to release MSI/MSI-X messages up to the parent bridge. */
1943 pcib_release_msi(device_t pcib, device_t dev, int count, int *irqs)
1947 bus = device_get_parent(pcib);
1948 return (PCIB_RELEASE_MSI(device_get_parent(bus), dev, count, irqs));
1951 /* Pass request to alloc an MSI-X message up to the parent bridge. */
1953 pcib_alloc_msix(device_t pcib, device_t dev, int *irq)
1955 struct pcib_softc *sc = device_get_softc(pcib);
1958 if (sc->flags & PCIB_DISABLE_MSIX)
1960 bus = device_get_parent(pcib);
1961 return (PCIB_ALLOC_MSIX(device_get_parent(bus), dev, irq));
1964 /* Pass request to release an MSI-X message up to the parent bridge. */
1966 pcib_release_msix(device_t pcib, device_t dev, int irq)
1970 bus = device_get_parent(pcib);
1971 return (PCIB_RELEASE_MSIX(device_get_parent(bus), dev, irq));
1974 /* Pass request to map MSI/MSI-X message up to parent bridge. */
1976 pcib_map_msi(device_t pcib, device_t dev, int irq, uint64_t *addr,
1982 bus = device_get_parent(pcib);
1983 error = PCIB_MAP_MSI(device_get_parent(bus), dev, irq, addr, data);
1987 pci_ht_map_msi(pcib, *addr);
1991 /* Pass request for device power state up to parent bridge. */
1993 pcib_power_for_sleep(device_t pcib, device_t dev, int *pstate)
1997 bus = device_get_parent(pcib);
1998 return (PCIB_POWER_FOR_SLEEP(bus, dev, pstate));
2002 pcib_ari_get_rid(device_t pcib, device_t dev)
2004 struct pcib_softc *sc;
2005 uint8_t bus, slot, func;
2007 sc = device_get_softc(pcib);
2009 if (sc->flags & PCIB_ENABLE_ARI) {
2010 bus = pci_get_bus(dev);
2011 func = pci_get_function(dev);
2013 return (PCI_ARI_RID(bus, func));
2015 bus = pci_get_bus(dev);
2016 slot = pci_get_slot(dev);
2017 func = pci_get_function(dev);
2019 return (PCI_RID(bus, slot, func));
2024 * Check that the downstream port (pcib) and the endpoint device (dev) both
2025 * support ARI. If so, enable it and return 0, otherwise return an error.
2028 pcib_try_enable_ari(device_t pcib, device_t dev)
2030 struct pcib_softc *sc;
2037 sc = device_get_softc(pcib);
2040 * ARI is controlled in a register in the PCIe capability structure.
2041 * If the downstream port does not have the PCIe capability structure
2042 * then it does not support ARI.
2044 error = pci_find_cap(pcib, PCIY_EXPRESS, &pcie_pos);
2048 /* Check that the PCIe port advertises ARI support. */
2049 cap2 = pci_read_config(pcib, pcie_pos + PCIER_DEVICE_CAP2, 4);
2050 if (!(cap2 & PCIEM_CAP2_ARI))
2054 * Check that the endpoint device advertises ARI support via the ARI
2055 * extended capability structure.
2057 error = pci_find_extcap(dev, PCIZ_ARI, &ari_cap_off);
2062 * Finally, check that the endpoint device supports the same version
2063 * of ARI that we do.
2065 ari_ver = pci_read_config(dev, ari_cap_off, 4);
2066 if (PCI_EXTCAP_VER(ari_ver) != PCIB_SUPPORTED_ARI_VER) {
2069 "Unsupported version of ARI (%d) detected\n",
2070 PCI_EXTCAP_VER(ari_ver));
2075 pcib_enable_ari(sc, pcie_pos);